Cell microprocessor

Cell is a Microprocessor architecture jointly developed by Sony Computer Entertainment, Toshiba, and IBM, an alliance known as "STI". The architectural design and first implementation were carried out at the STI Design Center in Austin, Texas over a four-year period beginning March 2001 on a budget reported by Sony as approaching United States dollar US$400 million.
Cell is shorthand for Cell Broadband Engine Architecture, commonly abbreviated in full or Cell BE in part. Cell combines a general-purpose Power Architecture "Multi-core (computing)" of modest performance with streamlined Coprocessor which greatly accelerate multimedia and Vector processing applications, as well as many other forms of dedicated computation.
The first major commercial application of Cell was in Sony's PlayStation 3 Video game console. Mercury Computer Systems has a dual Cell server, a dual Cell configuration, a rugged computer, and a PCI Express accelerator board available in different stages of production. Toshiba has announced plans to incorporate Cell in High-definition television sets.

PlayStation 3 to be used for military interests?

Recently, Mercury Computer Systems released its MultiCore Plus SDK for the PlayStation 3. The event is pretty notable because it is one of the very few third-party developments kits available for game consoles.

Mercury has said however, that they are not at all interested in games but rather in military interests citing the PlayStation's Cell processor as being a very powerful yet still pretty cheap platform.

Mercury is using the PS3's ability to load Linux and pairing it with its SDK to perform powerful tasks such as running a node in a computing cluster.

Beyond DDR3

XDR™2 Memory Architecture

The XDR™2 memory architecture is the world's fastest memory system solution capable of providing twice the peak bandwidth per device when compared to a GDDR5-based system. Further, the XDR2 memory architecture delivers this performance at 30% lower power than GDDR5 at equivalent bandwidth.

Designed for scalability, power efficiency and manufacturability, the XDR2 architecture is a complete memory solution ideally suited for high-performance gaming, graphics and multi-core compute applications.

Initial systems can achieve memory bandwidths of over 500GB/s into an SoC. Each XDR DRAM can deliver up to 38.4GB/s of peak bandwidth from a single, 4-byte-wide, 9.6Gbps XDR2 DRAM device, and the XDR2 architecture supports a roadmap to device bandwidths of over 50GB/s.

Capable of data rates of 6.4 to 12.8Gbps, the XDR2 architecture is the latest generation in the award-winning family of XDR products. With backwards compatibility to XDR DRAM, the XDR2 architecture is part of a continuously compatible roadmap, offering a path for both performance upgrades and system cost reductions.